1. Field of the Invention
This invention relates to data transmission and, more particularly, to transmitting data over a double data rate link.
2. Description of the Related Art
Double data rate links are becoming increasingly popular. On a double data rate link, data is transferred on both the rising and falling edges of a clock. As a result, the rate of data transmission may be effectively doubled compared to prior links, which typically receive data on either the rising or the falling edge of a clock in the receiver. Some double data rate links are source-synchronous links (also referred to as clock forwarding links), which transmit a clock signal in addition to data. Because the transmit clock is sent along with the data, the transmit clock remains in phase with the data as both propagate to the receiver. This in turn allows very high-speed data recovery at the receiver, minimizing errors due to set-up and hold violations.
Typically, even-sized data packets are transmitted over a double data rate link. For example, a double data rate link may include eight data lines and one clock line. Each clock edge, a new byte of data may be transferred over the link. Bytes within a word-sized packet may be transmitted over the link in the sequence byte 0-byte 7. If byte 0 is transmitted on the rising edge of the clock, bytes 0, 2, 4, and 6 may be transferred on rising edges and bytes 1, 3, 5, and 7 may be transferred on falling edges. Since the final byte in the packet is transmitted on the falling edge of the transmit clock, subsequently transferred packets will also have even bytes on rising edges and odd bytes on falling edges. Accordingly, a receiver may easily synchronize data packets to particular edges of the transmit clock.
When odd-sized data packets are transferred over a double data rate link, the clock edge on which a particular byte is received may vary from packet to packet. For example, if nine bytes are included in each packet, byte 0 of successive packets will be transferred on alternating even and odd transmit clock edges. For example, bytes 0, 2, 4, 6, and 8 of a first packet may be transferred on rising clock edges. Bytes 1, 3, 5, and 7 of that packet may be transferred on falling clock edges. Since the final byte of the packet is transferred on a rising clock edge, the first byte of the next packet will be transferred on a falling clock edge. Since each packet may begin on a different clock edge than the previous packet, receiver logic may be undesirably complex.